The present invention relates to an instruction handling sequence control system for use in a vector computer to issue and execute instructions without following the sequence of instruction executions designated by a program.
A system to increase the speed of instruction handling by dynamically determining the sequence of instruction handling and issuing instructions to the arithmetic unit and the main storage processing unit without following a program-designated sequence is used in computers for scalar processing. For details of this system, reference may be made to D. W. Anderson et al., "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling", IBM Journal of Research & Development, vol. 11, No. 1, IBM, January 1967, pp. 8-24, and S. Weiss et al., "Instruction Issue Logic for Pipelined Supercomputers", 11th Annual International Symposium on Computer, IEEE, 1984, pp. 110-118.
The computers controlling the sequence of instruction handling have means to detect collisions of the input/output operands and memory addresses of instructions, judge how the arithmetic unit and the main storage handling unit are used, and decide on the issue of instructions to the arithmetic unit and the main storage handling unit without following a programmed sequence. This instruction issuing system can be as well applied to vector computers as to scalar computers. In a vector computer, however, it is difficult to judge whether a plurality of memory referencing vector instructions can be supplied to the main storage handling unit in a sequence reverse to what is designated by a program. Thus, the store starting point address of a vector store instruction designated for programmed execution being represented by base1; the distance between the elements of the vector to be stored under the vector store instruction, by dist1; the length of the vector to be stored thereunder, by len1 (len1.gtoreq.1); the load starting point address of a vector load instruction designated for programmed execution after the vector store instruction being represented by base2; the distance between the elements of the vector to be loaded under said vector load instruction, by dist2; and the length of the vector to be loaded thereunder, by len2 (len2.gtoreq. 1), it is judged that the vector load instruction may reference the main store earlier than said vector store instruction only when the set of intersections between {base1, base1+dist1.times.1, base1+dist1.times.2, . . . , base1+dist1.times.(len1-1)}, which is the set of addresses to be stored under the vector store instruction, and {base2, base2+dist2.times.1, base2+dist2.times.2, . . . , base2+dist2.times.(len2-1)}, which is the set of addresses to be loaded under the vector load instruction, is void. It is difficult, however, to pass judgement in a short period of time on an arbitrary combination of bas1, dist1, len1 (len1.gtoreq.1), base2, dist2, len2 (len2.gtoreq.1).
In this connection, there is proposed, as applicable to cases permitting simple judgment, a method to determine the overlapping of address ranges by which referencing the main store by a vector load instruction ahead of a vector store instruction can be allowed if the set of intersections between {add1:base1.ltoreq.add1.ltoreq.(base1.times.dist1.times.(len1-1))} whose address set elements range from a store starting point address base1, designated by a preceding vector store instruction, to base1.times.dist1.times.(len1-1), the final store address of the same vector store instruction, and {add2:base2.ltoreq.add2.ltoreq.(base2.times.dist2.times.(len2-1))} whose address set elements range from a load starting point address base2, designated by a following vector load instruction, to base2+(len2-1).times.dist2, the final load address of the same vector load instruction, is void. While this method permits the needed judgment with comparative ease, the combinations of base1, dist1, len1 (len1.gtoreq.1), base2, dist2 and len2 (len2.gtoreq.1) allowing correct judgment of passability are limited. Thus the method to determine the overlapping of address ranges has the disadvantage that, out of the 24 possible sequential relationship among base1, last1, base2 and last2, at most the following eight:
(base1.ltoreq.last1.ltoreq.base2.ltoreq.last2) PA1 (base1.ltoreq.last1.ltoreq.last2.ltoreq.base2) PA1 (last1.ltoreq.base1.ltoreq.base2.ltoreq.last2) PA1 (last1.ltoreq.base1.ltoreq.last2.ltoreq.base2) PA1 (base2.ltoreq.last2.ltoreq.base1.ltoreq.last1) PA1 (last2.ltoreq.base2.ltoreq.base1.ltoreq.last1) PA1 (base2.ltoreq.last2.ltoreq.last1.ltoreq.base1) PA1 (last2.ltoreq.base2.ltoreq.last1.ltoreq.base1)
permit correct judgment, where base1 is the store starting point address of a vector store instruction designated for programmed execution; dist1, the inter-elemental distance of the vector to be stored under the vector store instruction; len1 (len1.gtoreq.1), the vector length to be stored thereunder; last1, the address of the final vector element to be stored thereunder; base2, the load starting point address of a vector load instruction designated for programmed execution after the vector store instruction; dist2, the inter-elemental distance of the vector to be loaded under the vector load instruction; len2 (len2.gtoreq.1), the vector length to be loaded thereunder; and last2, the address of the final vector element to be loaded thereunder.